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PE43701
Product Specification
Figure 20. Serial-Addressable Timing Diagram
Bits can either be set to logic high or logic low
*D[7] must be set to logic low
DI[6:0]
T DISU
T DIH
ADD[2:0]
VALID
P/S
T ASU
T PSSU
T AIH
T PSIH
SI
D[0]
D[1]
D[2]
D[3]
D[4]
D[5]
D[6]
*D[7]
A[0]
A[1]
A[2]
CLK
T SISU
T SIH
LE
T CLKL
T CLKH
T LESU
DO[6:0]
Figure 21. Latched-Parallel/Direct-Parallel Timing Diagram
P/S
T LEPW
T PD
VALID
DI[6:0]
T PSSU
VALID
T PSH
LE
DO[6:0]
T DISU
T LEPW
T DIPD
VALID
T PD
T DIH
Table 11. Serial-Addressable Interface
AC Characteristics
V DD = 3.3 or 5.0 V, -40° C < T A < 85° C, unless otherwise specified
Table 12. Parallel and Direct Interface
AC Characteristics
V DD = 3.3 or 5.0 V, -40° C < T A < 85° C, unless otherwise specified
Symbol
F CLK
T CLKH
T CLKL
T LESU
T LEPW
T SISU
T SIH
T DISU
T DIH
T ASU
Parameter
Serial clock frequency
Serial clock HIGH time
Serial clock LOW time
Last serial clock rising edge setup
time to Latch Enable rising edge
Latch Enable min. pulse width
Serial data setup time
Serial data hold time
Parallel data setup time
Parallel data hold time
Address setup time
Min
-
30
30
10
30
10
10
100
100
100
Max
10
-
-
-
-
-
-
-
-
-
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
Symbol
T LEPW
T DISU
T DIH
T PSSU
T PSIH
T PD
T DIPD
Parameter
Latch Enable minimum
pulse width
Parallel data setup time
Parallel data hold time
Parallel/Serial setup time
Parallel/Serial hold time
Digital register delay
(internal)
Digital register delay
(internal, direct mode only)
Min
30
100
100
100
100
-
-
Max
-
-
-
-
-
10
5
Unit
ns
ns
ns
ns
ns
ns
ns
T AH
T PSSU
T PSH
T PD
Address hold time
Parallel/Serial setup time
Parallel/Serial hold time
Digital register delay (internal)
100
100
100
-
-
-
-
10
ns
ns
ns
ns
Note:
f Clk is verified during the functional pattern test. Serial-
Addressable programming sections of the functional
pattern are clocked at 10 MHz to verify fclk specification.
Document No. 70-0243-06 │ www.psemi.com
?2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Page 9 of 13
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
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